资源列表
Para_to_Seril
- 用VHDL实现串并变换的程序，FPGA测试成功，正确变换。-String with VHDL implementation and transformation procedures, FPGA test successfully, the correct transformation.
12864
- 使用FPGA对12864模块进行驱动控制的程序-Use the FPGA to drive on the 12864 module control program
dianti
- 实现电梯的VERILOG 源程序，完成实现，有仿真波形-VERILOG source code to achieve the elevator to complete the implementation, a simulation waveform
ddr2_sdram
- xilinx spartan2 fpgaddr2控制代码，使用verilog编写，可综合-xilinx spartan2 fpgaddr2 control code, using verilog preparation, can be integrated
Taxi
- EDA课程设计出租车计价器的VHDL语言设计的程序 出租车计价器：5KM起计价，起始价5元，每公里1.2元；传感器输出脉冲为0.5m/个；每0.5km改变一次显示，且提前显示（只显示钱数）-EDA curriculum Taximeter the VHDL language design process Taximeter5KM from the valuationthe starting price of 5 yuan1.2 yuan per kilometersensor output
Phase_Meter
- 无正负的带显示的周期信号相位差测量实现的程序代码-Unsigned band show the periodic signal code phase measurement achieve
2010_electronic_competetion_PicoBlaze
- 2010年北京市电子设计大赛内部培训PPT，上面详细的说明了有关picoblaze软核的应用。-Electronic Design Competition 2010 Beijing house training PPT, the above detailed descr iption of the application of the picoblaze soft-core.
tlc5620_out_sin
- 用ＦＰＧＡ操纵ＴＬＣ５６２０DA转换器，用ＶＨＤＬ语言编写，调试通过，并输出正弦波。-Manipulation TLC5620DA converter with FPGA using VHDL language, debugging through, and the output sine wave.
matlab_tdm_example_sp2010
- 6位计数器 实现6位计数功能 很强大哦 实现6位计数功能 -6 Counter
VHDLqiangdaqi
- VHDL四路抢答器该任务分成七个模块进行设计，分别为：抢答器鉴别模块、抢答器计时模块、抢答器记分模块、分频模块、译码模块、数选模块、报警模块，最后是撰写顶层文件。-VHDL four Responder divided into seven modules of the design task, namely: Responder identification module, timing module Responder, Responder scoring module, frequency
verilog_pingpang
- verilog 语言的写的乒乓操作，通过两个寄存器实现。-verilog language, written in ping-pang operation, achieved through two registers.
notefortx_src
- 数字电视，清华大学关于dtmb调制器的 代码描述-Digital TV, Tsinghua University, the code on the dtmb modulator described