资源列表
8B10BEncodeDecode
- 基于FPGA的8B10B编解码程序，内含编码和解码文件-FPGA-based 8B10B decoding process, encode and decode files containing
CompletethedirectsequencespreadspectrumsystemPNpre
- 完成直接序列扩频系统的伪码精确同步，并用FPGA进行实现-Complete the direct sequence spread spectrum system PN precise synchronization, and implementation with FPGA for
TSE
- 利用SOPC Builder搭建三速率以太网基本构架，完成以太网功能。-SOPC Builder using the basic framework set up three speed Ethernet, Ethernet function to complete.
MP3
- MP3解码的ASIC全部过程，包换含c和vhdl代码，样例。-MP3 decoding ASIC whole process, shifting with c and vhdl code, sample.
dds
- 在quartus下的DDS设计，Verilog语言，可以产生正弦波、三角波、方波等，频率可调。-Under the DDS in quartus design, Verilog language, you can produce sine wave, triangle wave, square wave, frequency adjustable.
programtested7.27
- 可综合的信道估计模块，包括解OFDM，解导频，用于8x8，2048点的OFDM信号的信道估计-Channel estimation can be integrated module, including the solution OFDM, pilot solution for the 8x8, 2048 points of OFDM signals in channel estimation
CPLD_V105
- epm240系列cpld的配置文件，实现cpld对flash，uart和sdram的控制等-epm240 series cpld profile, to achieve cpld on the flash, uart and the sdram of the control
pli_handbook_examples_pc
- The Verilog PLI Handbook(contained code)
Synopsys-RTLSystemC
- synopsys的systemc和RTl书籍清晰电子版，专业权威的EDA公司的培训资料-synopsys of systemc and RTl clear electronic version of books, professional authority of the EDA company' s training materials
ALU
- 用VHDL硬件描述语言写的ALU设计，有加法，减法，乘法和除法等计算功能。-VHDL hardware descr iption language used to write the ALU design, there are addition, subtraction, multiplication and division such as computing.
m
- 由20位移位寄存器线性反馈产生的m序列的vhdl代码-20-bit shift register linear feedback sequence generated vhdl code m
fir_16
- 用Verilog写的fir滤波器，16阶8位位宽，看看吧-Written using Verilog fir filter, 16-order 8-bit wide, to see if it