资源列表
FPGA_CRC
- 用Quartus II 13.0 (32-bit)实现并行计算8位数据宽度的CRC16-CCITT循环冗余码，verilog HDL源代码，并有本人手工计算的原理。本程序已经过ModelSim-Altera模拟，仿真波形文件都在本文件内。-Calculated using the Quartus II 13.0 (32-bit) parallel 8-bit data width CRC16-CCITT cyclic redundancy code, verilog HDL source cod
A_PUF_Design
- 基于fpga的物理不可克隆函数（PUF）模块的实现-A PUF Design for Secure FPGA-Based Embedded Systems
graduate
- 基于fpga的IIR和FIR滤波器实现，里面有DA和AD模块，已经下载到板子上验证。-IIR and FIR filter fpga-based implementation, which has DA and AD modules have been downloaded to authenticate to the board.
dsp320vc33_20020210.tar
- dsp 320 in vhdl.code for sram also included.
phyjingjian
- 通过fpga对phy芯片88e1111进行控制，可改变工作模式，传输速度等。-By fpga control of phy chip 88e1111 can change the working mode, the transmission speed.
pingpangqiu
- 基于basys2的简单的乒乓球小游戏，通过ise13.4开发，使用语言VHDL，能够通过VGA在显示屏显示，能够实现双人对打，有计分功能。-Simple table tennis game, based on basys2 through ise13.4 development, using VHDL language, can through the VGA display shows, can achieve a double play, scoring function.
ds769_axi_slave_burst
- xilinx AXI4 slave burst 接口的介绍文档，有助于理解IP核-The introduction of xilinx AXI4 slave into the interface documentation
RGB-to-YCbCr[Verilog]
- 基于FPGA平台的颜色色彩空间转换 RGB to YCbCr-Based on the FPGA platform color RGB to YCbCr color space transformation
Quartus
- VERILOG AD采集程序 FIFO存储-VERILOG AD acquisition program FIFO memory
all_test_3
- FPGA芯片开发板对应器件测试程序，包括led，按键，AD/DA等多种器件-FPGA chip development board corresponding device testing procedures, including led, buttons, AD/DA and other devices
hello_sd
- 基于fpga verilog 语言和nios ii实现的spi模式下sd卡驱动，以及加入znfat文件系统的sd卡驱动，可读取sd卡内的文件。-Based on the language and under the fpga verilog realize spi mode nios ii sd card driver, and adding znfat sd card file system driver, you can read files sd card.
PCIIP-core
- 基于FPGA的PCI ip core 设计源代码，里面包含所有的fifo,状态机源代码，drives 驱动源代码。-“fifo_control.v” Module FIFO_CONTROL includes control logic for single FIFO. It consists of read and write address generation and full, almost full, empty and almost empty status generatio