资源列表
FSK
- FPGA实现FSK调制，带Modelsim仿真，实际系统测试通过，载波信号，信号频率等可调。-FPGA implementation FSK modulation with Modelsim simulation, the actual system test, the carrier signal, the signal frequency is adjustable.
MIPS_32numbers_32bits
- MIPS架构下的32位32个寄存器组的verilog源码-MIPS architecture 32 32 register banks verilog source
dds(9854)_test(sin_cos)(EP1C6)
- 通过FPGA控制DDS(AD9854)输出120M一下的双路正交信号，实现在通信和控制领域的应用。-Controlled by FPGA DDS (AD9854) output 120 m the dual orthogonal signal, realize the application in the field of communication and control.
jiajian
- 利用Verilog语言编写的按键实现数码管显示数字的加减，通过三个按键分别实现加1和减1操作 以及复位操作，BASYS2开发板验证。-Verilog language use buttons to achieve digital display digital subtraction achieve plus one and minus one operation and reset operation, BASYS2 development board were verified by thr
SDRAM-verilog
- SDRAM控制器.用verilog实现SDRAM的读写操作。-sdram coll
simple-pipeLine-CPU
- 简单的流水线CPU实现，基于MIPS指令集。-Simple pipelined CPU implementation, based on the MIPS instruction set.
t_sensor
- 数字温度计的Verilog实现，有时钟控制模块，显示模块，温度计控制模块。-digital temperature sensor
sss
- 使用Verilog语言编写源代码.调用一些基本的IP核，如DCM模块、DDS模块ChipScope模块、乘法器模块等来实现调制.最后通过编程并利用FPGA板子实现AM、DBS、SSB的调制。-Using Verilog language source code. Invoke some basic IP cores, such as DCM module, DDS module ChipScope modules, multiplier module to achieve modulation.
9854_VERILOG
- AD9854的FPGA程序，经过试验，全都好使，带有注释，方便开发-The FPGA program AD9854, tested, all so that, with the notes to facilitate the development of
avnet_edk12_4_xbd_files
- 安富利SP605开发板ISE12.4版本的XBD文件，里面包括了开发板所有的接口，包括硬件和软件设计-Avnet SP605 development board ISE12.4 version XBD file, which includes the development board all interfaces, including hardware and software design
LDPC_FPGA
- LDPC码的FPGA实现，大家相互学习下-the code of LDPC implementation by FPGA
cordic_exer
- 自己编写的CORDIC文件，总共6层，收敛于y轴，即求平方根和正切函数-the cordic verilog HDL file made by myself