资源列表
BCHdecode
- BCH(63,56) decode,verilog
mtspeed
- m法t法编码器测速 verilog语言 m法采样时间可调 t法间隔周期可调-m method t method m encoder velocity verilog language law law sampling time interval period adjustable adjustable t
is61lv25616
- 以is61lv25616为例，用verilog实现的SRAM-SRAM implemented verilog
LPC_Host
- LPC总线，主机模块代码，VHDL语言描述-LPC bus, the host code, VHDL language descr iption
CameraLink-source-code
- 基于FPGA的多路CameraLink数据的发送和接收程序源码-FPGA-based multi-CameraLink data sent and received program source code
USB3.0specification(chinese)
- USB3.0的中文技术规范，包含结构规范和电气规范，适合英文不佳的工程师参考设计。-Chinese USB3.0 specification, including structural and electrical specifications for reference design engineers with poor English.
verilog-Design
- 英文的verilog设计手册，内容详尽，专业-Verilog design manual in English, detailed, professional
CIEDE2000
- CIEDE2000计算实例，每个步骤都有，计算最新的色差公式-Ref: G. Sharma, W. Wu, E.N. Dalal,"THE CIEDE2000 COLOUR-DIFFERENCE FORMULA: Implementation Notes, Supplementary Test Data, and Mathematical Observations," submitted to COLOR RESEARCH AND APPLICATION, Jan 2004.
DAC5662
- DAC5662 verilog control code
SDH1
- SHD 详细设计,包含各种文档，以及VERILOG 源代码-SHD detailed design, including all documents
dac
- DA芯片输出控制 SPI协议 只写不读 FPGA用 verilog-DA-chip SPI protocol output control does not read write-only FPGA with verilog
hdlc_encode
- 基于Verilog的HDLC解码器。输出外接485进行差分输出。-HDLC-based Verilog decoder. Output of an external differential output 485.