资源列表
task2
- Verilog语言，可在QuartusII正确运行，实现远程控制系统，利用异步串行通信，PC发送数据FPGA接收，实现本地回环模式。-清华大学电子课程设计：Verilog language, you can QuartusII correctly, remote control systems, using asynchronous serial communication, PC to send data received FPGA to achieve the local loopback
calculator_final
- 清华大学电子课程设计：Verilog，QuartusII可正确运行，可下载到FPGA上，音乐计算器，完成两个三位数的运算，有注释，很强大-Verilog, QuartusII run correctly, can be downloaded to the FPGA, music, calculator, completed two three-digit operations, there are notes, very powerful! !
i2s_interface
- iis的verilog代码，符合iis协议标准，来自opencores网站。-iis the verilog code, in line with iis protocol standards, from opencores site.
filter
- 用vhdl硬件描述语言写的中值滤波器，主要对尖峰脉冲进行消除。在fpga上实现。-Vhdl hardware descr iption language used to write the median filter, mainly to eliminate spikes. Implemented on the fpga.
8B10B_decode
- 介绍8b/10b的编码与解码的详细流程，主要是基于FPGA的实现方法-8b/10b encoding and decoding described the detailed process
usb01
- ft2232的VERILOG工程应用实例。基于altera ep2c8芯片。能够到20MB/S的传输速度。
mips-cpu
- 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
MODELSYS
- 用verilog编写的运动自适应去隔行算法 表扩边缘检测 sad最小值编写-Verilog written with motion-adaptive deinterlacing algorithm detects the edge of the table to expand the minimum write sad
5B6B-codec
- verilog hdl实现5B6B编译码（光纤通信线路码型），包含了时钟发生器模块 ，信号源模块 ，编码模块 ，译码模块， 和检错模块，并通过modesim仿真验证。-verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal source modules, code modules, d
hi-3593_v-rev-a
- arinc429通信驱动文件，用于429通信-arinc429 communication driver files for 429 communications
NCVerilog_tutorial-chinese
- linux下cadence nc_verilog工具使用教程，中文的，很详细，很适合学习-tool under linux cadence nc_verilog tutorials, Chinese, very detailed, very suitable for learning
digital-lock
- vhdl课程设计电子密码锁的完整可执行程序，最终评为优秀-vhdl program designed electronic locks complete executable program, and ultimately as good