eee.std_logic_arith.all use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity PL_auto1 is port ( clk:in std_logic --系统时钟 set,get,sel,finish: in std_logic --设定、买、选择、完成信号 coin0,coin1: in std_logic --5角硬币、1元硬币 price,quan

1602的程序P1.1接RS，P1.2接en，P1.3接rw。P2.0~P2.7接的D0~D7。P2.6和P2.7这两个端口的SEL在复位以后默认是1，注意置0-Program P1.1 1602 pick RS, P1.2 then en, P1.3 pick rw. P2.0 ~ P2.7 pick of D0 ~ D7. SEL P2.6 and P2.7 of the two ports after reset default is 1, attention is set

利用STM8配置CC101实现FSK收发(Use the STM8 MCU to configure the CC1101, and work as FSK transceiver add the sel calibration for the datarate.)