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queues
- queue hardware deisgn with verilog
FIFO_8_8
- FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
fifo
- 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现先进先出的队列。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.
fifo_8_8
- 该程序实现的是8*8位的先进先出队列功能的存储器，已成功通过仿真。-Implementation of the program is 8* 8 bit FIFO queue memory function, has successfully passed the simulation.
Desktop.tar
- I ve implemented what oi believe to be a very usefull and easy way to understand the FIFO queue using a DPRAM
FIFO
- 先入先出队列(First Input First Output，FIFO)这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令。-FIFO queue (First Input First Output, FIFO) which is a traditional sequential execution method, first enter the command to finish and retire, only to follow the implementatio
queue
- 完成FIFO功能：the first element added to a queue will occur in the first place in the queue, the second element added to the queue will be after the first one-a kind of First-In-First-Out (FIFO) data structure，the first element added to a queue will occ
bank_manage
- 实现自动排队并完成叫号，设置一个排号按键，以及四个柜台用消号按键。当按下叫号键时，1.若队列不满，LCD显示"Your No.is 01!"的字样。2.若队列已排满，LCD显示"The queue is full,please wait"的字样。当按下消号键时，1.若队列无人，LCD显示"Sorry,the queue is empty!"的字样。2.若队列有人，蜂鸣器响，LCD显示如"No.01 come to No.1window,please!"的字样。-Automatic queuing
2
- opnet modeler 仿真中的passive queue pc_fifo实例-opnet modeler passive queue pc_fifo
Lab08
- 嚴格來說是verilog才對 但我找不到這環境 此code是用硬體去實現簡單的queue功能 可以合成在gate level 下也沒問題的 此外還有加上省電功能 有興趣可以參考一下-verilog for queue
arbiter2
- The logic design of an efficient and fast round robin arbiter in Verilog or any other HDL language relies on the capability to find the next requestor to grant without losing cycles and with minimal logical stages. Using the fastest logic constructs
grey-code--FIFO-IP-core
- 基于格雷码的FIFO的IP核，调试可用于通信接口的队列传输。-Gray code based on FIFO IP core, debugging can be used for communication queue transmission interface.
UART-IP-based-on-queue
- 基于队列传输的UART的IP核程序，已调试可直接使用。-Queue-based transmission of UART IP core procedures have been debugging can be used directly.
FIFO-queue-using-a-DPRAM
- FIFO queiue using DPRAM goog project
FIFO
- First Input First Output的缩写，先入先出队列，这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令。-The abbreviation of the first input first output, the first in first out queue, which is a traditional sequential execution method, first enter the command to finish and retire
Synchronous FIFO
- 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示(mplementation of a synchronous first in first out (FIFO) queue design with 16*8 RAM. A write FIFO that controls the data stream by writi