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electric-8.08
- The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including: * Custom IC layout * Schematic Capture (digital and analog) * Textual Languages such a
FPGA
- 将立体杂波图应用于气象杂波的CFAR处理，根据当前杂波环境的变化实时地产生杂内杂外标志，从而选择不同的信号处理支路处理当前气象杂波，提高了雷达的检测性能，降低了虚警概率。-Will be applied to three-dimensional meteorological clutter Clutter Map CFAR of treatment, according to the current clutter environment generated in real time with
adaptive_lms_equalizer_latest.tar
- In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random.
VHDLkejian
- EDA技术从某种意义上说：学习一种通过软件的方法来高效地完成硬件设计的计算机技术__------VHDL文字说明的系统的功能——系统逻辑描述（算法）——图、VHDL语言(用一套计算机能处理的语言来描述设计结果和设计要求)。 -EDA technology from a sense: to learn a software approach to efficiently complete the hardware design of computer technology __------ V
Verilogalotofexamples
- 关于VERilog 很多的例程，虽然不能处理比较大的应用，但是对于中小型的应用还是不错的-About VERilog lot of routines, although it can not handle larger applications, but applications for small and medium or good
MultiCLKCPU
- 本设计实现了多周期CPU的设计，运行环境是quatrus2；该多周期CPU可以处理22条32位指令（具体指令见源码，绝不坑人）。压缩包内含有源代码，程序模块表和实验报告以及详细的设计图，是学习verilog的好材料啊。-The Design and Implementation of a multi-cycle CPU design, operating environment is quatrus2 the multi-cycle CPU can handle 22 32 instructi
CrossClock
- This paper explores the fundamentals of signal synchronization and demonstrates circuits a designer can use to handle signals that cross clock domains!
time
- 几篇解读FPGA内部时序问题的好文章，从最近本的Tco,Tsu，Th等入门。一直到如何对时序进行约束，如何处理各种影响FPGA时钟的因素。如何读懂时序图（Interpreting the Timing Diagram） -FPGA internal timing problems read several good articles, from the most recent of Tco, Tsu, Th and other entry. How the timing has to be co
Adder_2bit
- Adder_2bit ，带进位处理的2位加法器 此实验中，实现了2bit宽度的加法运算，并带进位处理。加数与被加数分别以SW[3..2]和SW[1..0]来表示，加法的结果用数码管静态地显示出来。-Adder_2bit, with carry handle 2-bit adder this experiment, the realization of the addition operation 2bit width, and bit into the handle. Addend and
VGA_Controller
- 这个文件简直太好了，是个ip，费了好大的力气弄好的，可以挂在avalon总线上，用dma的方式将数据弄处理放在vga上进行显示。-This file is simply too good to be a ip, take a great effort things right, you can hang in the avalon bus, with the way the data get dma handle on the vga on the display.
LED_UART
- 介绍了UART的始初化，中断的使用，以及如何实现UART接收一段信号与处理-Introduced before the beginning of the UART, interrupt the use of, and how to handle UART receive a signal and
PS2USB-v2
- mega手柄 vusb to ps2 -mega handle vusb to ps2
Monitor_LRRV
- Quick test to handle VGA monitor enabling four colors on screen, Verilog Code Source using internal 50MHz clock signal.
MyDDR
- 分析FPGA如何控制DDR，这个方法是自己倍频而不是把倍频过程放进IPCORE里面处理-Analysis of how to control the FPGA DDR, this method is its frequency multiplier rather than the process inside the handle into the IPCORE
handset
- 利用硬件描述语言vhdl模拟实现与9针ps2手柄的串行通信，完成手柄输入信号的采集。-Vhdl simulation using hardware descr iption language to achieve ps2 with 9-pin serial communication handle, the handle to complete the input signal acquisition.
Tutorials
- Mentor graphics FPGA设计软件DK design suite PDK tutorial,该软件是基于high level synthesis，使用handle c设计。-Mentor graphics FPGA design software DK design suite PDKs the tutorial, the software is based on high level synthesis, using the handle c design.
fast-crc_latest.tar
- A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is presented. The design can handle 5 different channels at an input rate of 2Gbps each (the total output throughput is 5x4Gbps.)
windows-script
- 在window平台，采用脚本TCL来编译fpga的经典例子。具体的写法，见工程中的ise_flow.bat文件。如果在工作站来处理更块-In the window platform, using classic example TCL scr ipt to compile the fpga. Specific wording, see the project ise_flow.bat file. If the workstation to handle more blocks
Adder_16bit_2b
- 這是由我自己寫的16位元可處理2補數的加法器,希望能提供同學們課業上的好幫助-It was written by myself 16 yuan can handle two' s complement adder, hoping to provide better help students on academic
pong
- Simple pong VGA game implemented in VHDL. It can be used as example for FPGA-programmers to show how handle VGA displaying with FGPA device.