资源列表
wenjian
- PPM调制可见光通信系统，fpga，VHDL语言-PPMmodulation in visiable lighting communication system，VHDL FPGA
ethernet(MAC)verilog-langue
- 用veriolog编写以太网控制器（ＭＡＣ）-ｅｔｈｅｒｎｅｔ MAC of verilog
src
- verilog AD采样源代码，自己参照例程编写-verilog AD
SystemVerilog
- System Verilog中英文资料大全（pdf文档）-System Verilog Sourcebooks of Chinese and English (pdf document)
CIC-NCO-HB-FIR
- 数字下变频的论文，包含各个模块的设计，其中有CIC,HB,FIR,NCO等模块和源代码。-Digital down conversion papers, including the design of each module, including CIC, HB, FIR, NCO, modules and source code.
spram
- 基于altera fpga 的单口ram ip核的应用实例，包含整个工程和moselsim仿真，数据，写使能，地址都是用模块来产生的。-Altera fpga single port ram the ip core application instance, contains the entire engineering and moselsim of simulation data, Write Enable, addresses are generated by the module.
wola
- WOLA polyphase filter加权跌接累加FFT信道化技术-WOLA polyphase filter bank
sopc--dianti
- 设计一个三层楼自动电梯控制器，电梯内有三个输入按钮响应用户的上下楼层请求，并有七段数码管显示电梯当前所在楼层位置；在每层电梯入口处设有请求按钮开关，指示用户的上或下的请求。由LED灯显示电梯的上下运动情况和关门信息。-Design a three floors to be automatic elevator controller, elevator there are three buttons respond to user input the fluctuation floor reque
divide
- divide模块，实现除法功能。该module是用Verilog编写的，压缩包里包括了设计程序以及测试程序（testbench）。-divide module, the division function. The module is written in Verilog, compression bag, including the design process and testing process Sequence (testbench).
calender
- 这是用Verilog语言编写的万年历源代码，其中以小时为最小单位，可以区分闰年。有瑕疵还望海涵。-This is the calendar source code written in Verilog language, which hour is the smallest unit that can differentiate between leap years.
SGvga
- 基于System Generator 实现Xilinx FGPA的VGA显示模块，板块Nexys™ 3 Spartan-6 FPGA Board，可以直接把.bit文件下进去进行。 具体说明可以参考本人博客：http://www.openhw.org/wenlong0601/blog/12-03/239390_f7ef3.html-Based on the System Generator Xilinx FGPA VGA display module, the plate Nexy
Fuzzy_PID
- 用VHDL语言编写的模糊PID程序代码。成功调试，运行良好。-The source code of Fuzzy_pid in VHDL.Simulation was successful.