资源列表
Division
- Verilog hdl 除法综合仿真实现，另包含测试文件-Verilog hdl Division
baheyouxiji
- 用vhdl实验板子实现用led灯和按钮实现拔河游戏，通过按键快慢来决定灯的移动顺序，从而获胜-bahe game for led
CPU
- 东南大学COA下实验设计CPU完整程序，可以在RAM中写程序并可观察各个输出的波形，用于检验。-south-east university COA II the design cpu lesson which you can write your own program in the cpu and also can chack the wave
111
- 烟感探测器设计应用笔记,真好，真的很完整的设计应用笔记-Smoke detector design application notes, nice, really complete design application notes
C8051F120-DFT
- c8051f120 fft 样例程序,全部通过测试,可放心使用-c8051f120 fft
baseband_modulation_coef_gain
- CPM调制定点增益模块，完成CPM的调制指数确定-Phase locked loop demodulation module, for CPM modulation demodulation front end
VCO
- 压控振荡器的FPGA实现，Verilog语言完成。编译环境 ISE 13.2-The vco FPGA realizing, Verilog language completed. Compile environment ISE 13.2
Example-b4-1
- 1. 定制一个双端口RAM，DualPortRAM 2. 在顶层工程中实例化这个RAM 3. 实现这个工程，在Quartus II仿真器中做门级仿真 4. 在ModelSim中对这个工程进行RTL级仿真 -Customize a dual port RAM, DualPortRAM On the top floor of the RAM engineering instantiation To realize the project, in Quartus II simu
TLC_5620_sin
- 利用TLC5620产生正弦波，频率47HZ，幅值2.08-Use TLC5620 produce sine wave
encoding-decoding
- 卷积码编码译码程序以及其modelsim仿真波形文件等-Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file
OneD_DCT8
- 一维DCT变换，使用Verilog ＨＤＬ语言实现。有ＳＹｎｐｌｉｆｙ编译脚本-One-dimensional DCT, using the Verilog HDL language to achieve. The SYnplify compiled scr ipt
CPLD-Three-voting
- CPLD/FPGA 设计实例手册 用VHDL语言设计三人表决器 用原理图输入的方式设计三人表决器 用verilog-HDL语言设计三人表决器-CPLD/FPGA design example manual Three of the voting machine VHDL language Schematic design of a three-member voting Verilog-HDL language design three-member voti