资源列表
adder8
- 8位加法器源代码，vivado实现编写。-8 adder Source, vivado achieve write.
AFE0064
- AFE0064模拟前端芯片代码，使用verilog语言实现。-TI AFE0064 analog-front-end code with the verilog language
music
- 利用PWM使蜂鸣器产生音乐的verilog源代码及《友谊地久天长》的电路设计-Generates a PWM buzzer music verilog source code and Auld Lang Syne circuit design
H.264-for-FPGA
- This Book describe about H.264 encoder using Verilog HDL
TSMC
- TCBN65LPBWP7T VERSION 200A tsmc CLN65LP : 65nm CMOS LOGIC Low Power
Random_Derandom
- 通信中加扰/解扰算法。FPGA源代码，verilogHDL语言实现，包含测试程序。-Perturbation/perturbation algorithm. FPGA source code, verilogHDL language implementation, including test procedures.
Interleaver_Deinterleaver
- 通信中卷积交织/解交织FPGA源程序，采用verilogHDL代码实现，包含测试程序，经过验证。-Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.
FPGA_on_radar
- FPGA技术 北京理工大学PPT 在雷达上的应用-PPT FPGA technology used in the radar
uart_fifo
- 一份带有FIFO缓存的UART源码，采用verilog编写，实现批量数据的传输，数据缓存量可以通过修改源码中的FIFO的深度来改变。-This is a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.
xapp592
- sdi的发送和接收程序，使用XILINX ip核实现-SDI sending and receiving procedures, the use of XILINX nuclear IP
pipline_lms_and_rls_verilog
- 流水线LMS，和RLS算法的Verilog代码，用于自适应信号处理的FPGA实现。-The Verilog code about fir_pipline_lms and fir_rls. They commonly used in adaptive signal processing in FPGA platform.
min-sel
- 用来找到输入数据中的最小值和第二小值得verilog源码，可仿真-Used to find the minimum value of the input data and the second small worth verilog source code, can be emulated