资源列表
spdif
- spdif接口，用于高音质音频数据传输。代码实现了数据接收和发送。-spdif interface for high-quality audio data transmission
Motion_control
- 基于FPGA的运动控制系统设计，包含位置、速度控制等-motion control
ml605_pcie_x4_gen2
- 使用与xilinx的ml605套件的pcie核程序，芯片 型号是v6系列的4通道的pcie设计。内部包括pcie ip核和用户端程序。已亲测。-Xilinx ml605 using the kit pcie nuclear program, chip model is v6 series of 4-channel pcie design. Internal including pcie ip core and client programs. It has been pro-test.
Limi
- 用VHDL设计一个6位二进制计数器：用VHDL设计一个6位二进制计数器-VHDL design with a 6-bit binary counter
tb_axi4
- 介绍如何使用vivado来调用和封装IP核，测试AXI4总线的三种功能协议。-It describes how to use vivado to call and package IP core test three functions AXI4 bus protocol.
video_center_scan_scaler_alpha_blend
- 本工程实现两路视频信号阿尔法通道混合(alpha blend), 视频信号黑点中心 点扫描定位，期间用到视频帧缓存（frame cache）、视频信号缩放(scaler)等，且用到ram、DDR2等作为缓存，是很值得参考的视频图像处理工程。-scaler,alpha blend,ddr2 controller,center scan, frame cache, dpram, etc by verilog, include code and discr iption
can_pci
- 四通道CAN控制器的实现代码，可实现EP3C25F324控制4路SJA1000芯片，并在FPGA内部实现对SJA1000的初始化过程-source code for an four channel CAN controller in FPGA.
CFO
- zedboard/AD9361平台进行无线收发，在接收端进行频偏估计和补偿的Verilog参考代码。-zedboard/AD9361 platform for wireless transceiver, the receiver frequency offset estimation and compensation, you can refer to the Verilog code.
myfpga
- 这个是经典的FPGA的相关的乘法器，除法器的代码，还有别的可用的资料，都是网络上攒的，并且真的是非常经典-This is a classic of the relevant multiplier divider FPGA code, as well as other available information, are saved on the network, and really is very classic
value_to_ascii
- 使用Verilog HDL 进行数值与字符ASCII码的转化，实现串口正确显示字符，编程环境Quartus -Use Verilog HDL to numerically with ASCII characters transformation, realize serial display character correctly, Quartus ii programming environment
FM_T
- 一个简单的FM调制模块，FM发射，用Verilog编写，基于Xilinx SPARTAN6 XC6LX9开发-A simple FM modulation modules for FM transmitter, using Verilog prepared, based on XILINX SPARTAN6 XC6LX9 Development
Quadrature-modulate-design
- FPGA正交调制设计Verilog程序代码-FPGA Orthogonal modulation design procedure code