资源列表
16bits_multiplier
- 这是一个有符号的16位乘法器的设计，包含详细的设计报告和全部的verilog代码。乘法器采用booth编码，4-2压缩，超前进位结构-This is a signed 16-bit multiplier design, detailed design reports and contains all of the verilog code. Multiplier using booth encoding ,4-2 compression, lookahead structure
state_machine-for-charging
- 利用有限状态机实现的投币式充电仪的模拟电路-Finite state machine coin-charging instrument analog circuits
data_recovery
- 通过数据恢复时钟的例子教程，对研究这类原理很有帮助哦-data clock decover xilinx example
bujindianji
- FPGA实现步进电机控制源代码。通过脉冲信号控制，产生一定频率脉冲的信号（脉冲频率用来控制速度），经过信号隔离放大（达到驱动电机的电压）来驱动控制步进电机-FPGA Implementation of stepper motor control source code. Controlled by the pulse signal, generating a frequency pulse signal (pulse frequency is used to control speed), vi
EX4
- 基于FPGA的16位乘法器，入门的可以好好看看。-FPGA-based 16-bit multiplier, getting started can be a good look.
zycolorled
- 采用EDA技术，使用Quartus软件实现了彩灯的控制控制器的设计与实现-Using EDA technology, using Quartus software control to achieve a lantern controller design and implementation
FPGA_UART
- FPGA实现UART串口通信协议 采用VHDL语言，顶层文件采用原理图的方式，简洁直观-FPGA Implementation of UART serial communication protocol
SRAM
- 使用Verilog语言编写的SRAM读写程序,不用添加IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-SRAM using Verilog language literacy program, do not add the IP core in Xilinx Spartan-6 run through, is a very good program Verlog
static-timing-analyze
- 特权同学主讲的FPGA设计的时序约束专题（STA部分）-Speaker privileged classmates timing constraints for FPGA design topics (STA section)
itc99-poli2-vhd.tar
- VHDL source code of the ITC -VHDL source code of the ITC 99
斐波那契数列Verilog实现
- 斐波那契数列Verilog实现
myproj
- 使用vhdl语言设计波形发生器，产生正弦波，方波，三角波，锯齿波，实现频率，幅度可调。项目包附有设计说明和资料。-Waveform generator using vhdl language design, produce sine, square, triangle, ramp, realize the frequency, amplitude adjustable. Project package with design specifications and data.