资源列表
sgmii_latest[1].tar
- 这个工程应用于千兆网传输的物理代码子层，同时也用于SGMII接口。两者不同之处是自动协商时链接定时器和控制信息。-This core implements Physical Coding Sublayer of 1000BaseX transmission (IEEE 802.3 Clause36 and 37). This core can also be used for SGMII interface as this interface leverages 1000BaseX PCS.
Sdram_Control_8Port
- 用verilog写的8端口SDRAM模块-8-port SDRAM module
encoder104
- 独热码到二进制代码的转换即10输入4输出的二进制编码器的verilog程序。-One-hot code to binary code conversion, or 10 inputs 4 outputs the binary encoder verilog program.
Cont_THS1207
- FPGA控制THS1207多通道ADC的verilog源代码-FPGA control THS1207 multi-channel ADC' s verilog source code
AN66806
- 提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码-Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code
clk_DCM_50to75MHz
- 调用ISE010.1的IP核DCM来实现频率倍增，本程序实现的是50MHz到75MHz的倍增，开发者可以根据DCM的参数设置实现不同频率的倍增-Call ISE010.1 IP core DCM to achieve frequency doubling, the program is 50MHz to 75MHz multiplication, developers can implement different parameter settings of DCM frequency mult
chengfaleijia
- verilog 乘法累加器 包括工程项目及仿真波形图-verilog multiplier-accumulator including the project and the simulation waveform
signed_integer_divider_latest.tar
- VERILOG IMPLEMENTATION OF SIGNED INTEGER DIVIDER
spramipcore
- 使用vhdl语言在fpga环境下实现ip core spram-Environment in fpga vhdl language used to achieve ip core spram
chengfaqi
- 基于fpga的乘法器设计 已经验证请放心下载-Fpga-based multiplier design has been verified, please rest assured download
fpga
- FPGA控制DS18B20温度测量及显示,温度范围-20℃至100℃，精度0.1℃。数据刷新周期小于1秒。产生警报 -FPGA control DS18B20 temperature measurement and display
new-project
- 基于verilog的贪吃蛇 苹果同屏幕同时出现，贪吃蛇吃完所有苹果游戏结束，贪吃蛇的另一种写法-Based on the same screen verilog Snake Apple simultaneously, Snake eating all the apples end of the game, Snake' s another way