资源列表
myFPGA
- FPGA芯片测量两路信号的相位差，将相差信号以脉冲数的形式发出-FPGA measure the difference between two signals’signal
bluespec-h264_latest.tar
- H.264硬件视频解码，采用verilog代码设计，支持1.5M时钟下30bps的QCIF分辨率的实时视频解码-H. 264 hardware video decoder, use verilog code design, support under 1.5 M clock 30 BPS QCIF resolution of real-time video decoding
SDRAM_Test5
- 基于EP1C12Q240C8的红色飓风二代FPGA开发板的SDRAM测试程序，含有写入和读出FIFO，串口UART,数据发生模块。-Based EP1C12Q240C8 a red hurricane II FPGA development board SDRAM test program, containing written and read FIFO, serial UART, data generation module.
fpga_test_DA_AD
- 用于全国大学生电子设计大赛，一个基于FPGA平台的DA_AD程序。-For National Undergraduate Electronic Design Contest, an FPGA-based platform DA_AD program.
The-use-of-under-the-EDK-chipscope
- EDK下chipscope的使用，可以实时监控设计中的信号变化-EDK under chipscope use of real-time monitoring can change the design of the signal
usbtoiic
- usb转I2C接口的基于verilog的源码以及仿真结果等-usb to I2C Interface based verilog source and simulation results, etc.
LPC-program-CPLD
- 使用quartus开发。该程序通过VHDL语言实现了LPC时序。控制了2个LED数码管，通过读取LPC总线的上BIOS的数据，实现了计算机排故的POST卡功能。-Use quartus development. The program through the VHDL language to achieve a LPC timing. Control of the two LED digital tube, by reading the BIOS on the LPC bus data to a
ug_rsii
- Reed-Solomon II MegaCore Function user guide，altera的RS II编解码的宏功能模块的用户手册，是RS的升级版的IP，但大体使用一样。-Reed-Solomon II MegaCore Function user guide, altera s RS II codec macro function module user manual is an upgraded version of the RS s IP, but generally use
emifa_ram
- FPGA与DSP的EMIF通信，EMIF的RAM这方面相应的程序-FPGA and DSP EMIF communication
jpegencode_latest.tar
- fpga verilog 实现jpeg ip核编码器-fpga verilog forjpeg encode ipcore
FPGA
- verilog编写的QPSK发射机的ＦＰＧＡ部分，已经过验证，完全达到要求。调制矢量误差４％-QPSK transmitter verilog prepared by the FPGA portion, has been proven, fully meet the requirements. Modulation vector error of 4
FPGA(QII)
- 数字信号发生器，FPGA做的仿真程序，包含三角波、锯齿波、正弦波、方波等共六种波形。-FPGA AND alter SIN SAN JIAO BO JUCHIBO FANG BO