资源列表
GuessGame
- VHDL猜数游戏，系统生成随机数，操作者输入猜测的数字，系统给出输入数字与生成数字的大小关系，并统计猜测次数。可以下板使用-VHDL guessing game, the system generates a random number to guess the number of operator input, digital input and generating system gives the magnitude relationship between the digital and
verilog-montgomery-RSA
- 基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件-Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file
4answer
- 四路抢答器,实现抢答功能，采用verilog编程，代码简单易懂-four way of answer machine
74LS160jishuqi
- 74ls160十进制可预置计数器VHDL语言代码-74ls160 decimal VHDL language code can be preset counter
AXI_Master_FSM
- AXI Master, is implement with FSM
FPGADM9000AVerilog
- FPGA控制DM9000A进行以太网数据收发的Verilog实现-FPGA control DM9000A Ethernet data transceiver Verilog realize
uvm_switch_8
- 使用uvm验证环境搭建的testbench，主要验证switch的功能。可以学习uvm的简单功能-use uvm set up testbench ,the mainly focuse is verification swtich,you can learning uvm sample fucntion
GF-(q)-multiplier-design
- 伽罗华域GF（q）乘法器设计,FPGA实现-Galois field GF (q) multiplier design, FPGA realization
1111-Sequence-Detection
- 1111序列检测的设计VHDL代码，用状态机实现111序列检测的设计，如果检测到正确的序列，则led灯亮起，否则熄灭-1111 Sequence Detection design VHDL code, using the state machine to achieve 111 Sequence Detection design, if it detects the correct sequence, led lights, otherwise extinguished
ALINX9226_DB4CE15
- 这是AD9226的驱动程序，是12位的AD转换速率可以达到65M，FPGA用的是Altera的芯片相信你可以从中找到你想要的。-This is the AD9226 driver, 12-bit AD conversion rate can reach 65M, FPGA using Altera' s chips believe you can find what you want.
iq_balance
- 调整iq幅度不平衡的模块，可以解决载漏和边带问题。-Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.
PCI9054
- PCI9054控制器+乒乓SRAM读写控制器，是一份很好的初期学习程序，很简单 易懂-PCI9054 controller+ ping-pong SRAM write controller, is a very good early learning program, it is easy to understand