资源列表
Lab_02
- Verilog 3-to-8 Decoder on Spartan3E. Use 3 switches (SW[2:0]) as inputs. Keep SW[2] as MSB. Use 8 LEDs (LD[7:0]) as decoded outputs. i.e. if all input switches are turned off, LD0 should light up.
ds
- Verilog语言，实现移相,输入方波TA，输出移相后T-Phase shifted square wave TA, the phase-shifted output TAA
SOUND_PLAY6
- WM8731芯片的音效处理verilog代码， WM8731芯片是音频ADC\DAC芯片-WM8731 audio processing chip verilog code, WM8731 chip audio ADC \ DAC chip
Quartus-II-13.1-and-Verilog
- Quartus II 13.1的安装破解及第一个Verilog 程序的实现。-Quartus II 13.1 installation and the first to achieve break Verilog program.
HC-SR04
- HC-SR04超声波测距Verilog驱动程序，包含了驱动代码和测试程序，其中驱动程序输出的是回响高电平持续的时间长度，单位us，测量精度高达0.17mm，程序改进过很多次，本次的程序应该没什么问题了。-HC-SR04 Ultrasonic Ranging Verilog drivers, including the driver code and test procedures, which the driver sustained high output is echoed the leng
video_stream_scaler_latest.tar
- 图像放大程序，自带测试程序及说明，欢迎使用-Image amplification procedures, test procedures and comes with instructions, welcome
altfp_matrix_mult
- 浮点数 矩阵乘法模块 verilog语言编写 可直接调用-Floating-point matrix multiplication module can directly call verilog language
fm(912)
- 利用altera的FPGA，采用DDS原理实现FM调试，调试系数可改变，并通过DA变换输出，仿真以及下板测试成功-The use altera FPGA, using the DDS principle to achieve FM debugging, debugging coefficient can be changed through DA conversion output, simulation, and the lower plate test is successful
H.264_verilog
- 基于verilog的H.264视频压缩技术的源代码，包括verilog源代码，以及仿真波形文件，希望对大家有用-verilog h.264
hdmi_demo
- 基于verilog的HDMI接口传输的参考设计，希望对大家有用-verilog hdmi reference design
PCIE_DMA_DDR3_verilog_design
- 基于xilinx fpga的pci-e到dma再到ddr3的数据传输完整设计-PCIE_DMA_DDR3 verilog reference design
millisecond_counter
- 基于Spartan6写的fpga秒表，可以在七段译码管上显示，而且用按键来实现秒表的计时开始，停止，累加。而且该项目是移动信息工程学院的课程项目之一，希望对有需要的人有帮助-Fpga based Spartan6 write stopwatch that can be displayed on the seven-segment decoder pipes, and use the keys to achieve the stopwatch start, stop, accumulate. An